Senior Verification Engineer - MEMS Precision Timing

European Tech Recruit • Netherlands

Visa Sponsorship Relocation

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AI Summary

Develop SystemVerilog and UVM-based verification environments for analog and mixed-signal MEMS circuits. Define verification plans, write assertions, and manage simulation debugging for tape-out sign-off. Requires 6+ years of semiconductor verification experience and proficiency in SystemVerilog and scripting languages.

Key Highlights

Specialized role in MEMS precision timing for a market-leading semiconductor company

Focus on analog and mixed-signal verification using SystemVerilog and UVM

Visa and relocation support offered for candidates based in Delft, The Netherlands

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Key Responsibilities

Develop SV-RNM models for both analog and mixed-signal circuits

Develop verification plan from chip or block specifications

Develop UVM-based verification environment including scoreboards, monitors, and sequencers

Develop digital-top verification in System Verilog

Define and write System Verilog Assertions (SVA)

Define and write functional coverages and covergroups

Run simulations and debug simulation results

Review verification results for Tape-out sign-off

Communicate with stakeholders to facilitate teamwork and efficient sharing of information

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Technical Skills Required

SystemVerilog UVM Python

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Benefits & Perks

Visa support

Relocation support

Job Description

Sr. Verification Engineer

A fantastic opportunity for an experienced Verification Engineer to join a market leading Semiconductor company, who specialise in MEMS precision timing.

This role will be performed alongside the team in Delft (The Netherlands), and the company can offer Visa and Relocation Support where required.

Responsibilities:

• Developing SV-RNM models for both analog and mixed-signal circuits

• Developing verification plan from chip or block specifications

• Developing UVM-based verification environment (scoreboards, monitors, sequencers, etc.)

• Developing digital-top verification in System Verilog

• Defining and writing System Verilog Assertions (SVA)

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