Senior Verification Engineer

European Tech Recruit • Netherlands

Visa Sponsorship Relocation

This Job is No Longer Active This position is no longer accepting applications

AI Summary

Join a market leading Semiconductor company as a Senior Verification Engineer to develop SV-RNM models, verification plans, and UVM-based verification environments. The role requires proficiency in SystemVerilog, scripting languages, and analog schematic design. The company offers relocation support and visa sponsorship.

Key Highlights

Develop SV-RNM models for analog and mixed-signal circuits

Create verification plans from chip or block specifications

Design UVM-based verification environments

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Key Responsibilities

Developing SV-RNM models for both analog and mixed-signal circuits

Developing verification plan from chip or block specifications

Developing UVM-based verification environment (scoreboards, monitors, sequencers, etc.)

Developing digital-top verification in System Verilog

Defining and writing System Verilog Assertions (SVA)

Defining and writing functional coverages and covergroups

Running simulations and debugging simulation results

Reviewing verification results for Tape-out sign-off

Communicating with stakeholders (design/test/verification) to facilitate teamwork and efficient sharing of information and exchange of ideas

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Technical Skills Required

SystemVerilog SystemVerilog OOP Perl Python UVM SystemVerilog Assertions (SVA) Analog schematic design Cadence Virtuoso Verilog

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Benefits & Perks

Relocation support

Visa sponsorship

Job Description

Sr. Verification Engineer

A fantastic opportunity for an experienced Verification Engineer to join a market leading Semiconductor company, who specialise in MEMS precision timing.

This role will be performed alongside the team in Delft (The Netherlands), and the company can offer Visa and Relocation Support where required.

Responsibilities:

• Developing SV-RNM models for both analog and mixed-signal circuits

• Developing verification plan from chip or block specifications

• Developing UVM-based verification environment (scoreboards, monitors, sequencers, etc.)

• Developing digital-top verification in System Verilog

• Defining and writing System Verilog Assertions (SVA)

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