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Senior/Staff/Principal Physical IC Design Engineer (ASIC)
Visa Sponsorship
Relocation
AI Summary
Lead physical implementation of advanced ASIC designs from RTL to tape-out, optimizing timing closure, power integrity, and clock networks. Collaborate with cross-functional teams to deliver high-performance silicon for AI, ML, and data center applications. Requires deep expertise in full-cycle physical design, scripting, and methodology improvements.
Key Highlights
Cutting-edge ASIC development for AI, ML, networking, and data center applications
Full-cycle physical design responsibility from RTL to tape-out with timing closure ownership
Opportunity for relocation assistance to San Jose, CA or Colorado Springs, CO
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Key Responsibilities
Drive physical implementation activities throughout the ASIC development lifecycle, including RTL synthesis and place-and-route
Perform timing analysis, physical verification, and achieve timing closure for complex designs
Develop and optimize clock tree architectures, floorplans, and physical layouts for high-performance silicon
Execute EM/IR analysis and implement design optimizations to meet power integrity and signal integrity requirements
Collaborate with RTL and design engineering teams to resolve implementation challenges and support tape-out goals
Support methodology improvements, automation efforts, and design flow enhancements
Technical Skills Required
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Benefits & Perks
Health, dental, and vision insurance
Life and disability insurance
401k with 6% match
ESPP (Employee Stock Purchase Plan)
Flexible/Unlimited PTO
Annual bonus (15-30%)
Generous stock compensation
FSA and HSA
Visa sponsorship for qualified candidates
Job Description
Physical IC Design Engineer (Senior, Staff or Principal level)
Locations: San Jose, CA or Colorado Springs, CO (relocation offered)
Compensation (base, bonus + stock):
Senior Engineer up to $280-300k, Staff up to $400k, Principal up to $580k and possibly Master Engineer which is up to $800k total comp.
Introduction
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