Senior/Staff/Principal RTL IC Design Engineer (AI Infrastructure)

CyberCoders • United State

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AI Summary

Lead the design and optimization of advanced semiconductor RTL for next-gen AI, ML, and hyperscale data center infrastructure. Own critical digital IC development, from microarchitecture to silicon validation, collaborating across engineering teams. Drive timing closure, debug complex designs, and shape cutting-edge ASIC solutions with high impact.

Key Highlights

Work on AI/ML infrastructure silicon shaping next-gen computing and cloud technologies

Own full RTL design lifecycle from architecture to silicon bring-up and post-silicon validation

Competitive compensation with base + bonus + RSUs (up to $580k total for Principal level)

Key Responsibilities

Analyze architecture specifications and lead technical reviews for advanced semiconductor products

Develop microarchitecture and detailed RTL design documentation for high-performance digital ICs

Design and implement complex RTL (clock domain crossings, pipelined architectures, low-power solutions) using Verilog/SystemVerilog

Drive RTL optimization efforts to achieve timing, power, and performance goals

Debug and resolve complex design issues throughout the ASIC development lifecycle

Collaborate with verification, firmware, software, emulation, and validation teams

Support silicon bring-up and post-silicon validation activities in the lab

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Technical Skills Required

Verilog/SystemVerilog Digital IC Design ASIC/SoC Development

Benefits & Perks

Health, dental, and vision insurance

Life and disability insurance

401k with 6% match

Annual bonus (15-30%)

Stock options (ESPP)

Flexible/Unlimited PTO

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Nice to Have

PCIe protocol experience

CXL protocol knowledge

AMBA protocols (AXI, AHB, APB) familiarity

PCIe switch architecture experience

Storage/RAID or high-performance data movement solutions experience

Job Description

RTL IC Design Engineer (Senior, Staff or Principal)

Compensation:

For Senior - up to approx $280k total comp ($120-160k base, 20% bonus + RSUs)

For Staff - up to approx $400k total comp ($150-190k base, 25% bonus + RSUs)

For Principal - up to approx $580k total comp ($180-240k base, 30% bonus + RSUs)

Shape the Future of AI Infrastructure

Join an industry-leading engineering team developing the high-performance silicon that powers next-generation AI, machine learning, cloud computing, and hyperscale data center infrastructure. This is an opportunity to work on complex, cutting-edge ASIC designs that sit at the heart of some of the world's most demanding computing environments.

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