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Senior/Staff/Principal Physical IC Design Engineer (ASIC)

CyberCoders • United State
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Lead physical implementation of advanced ASIC designs from RTL to tape-out, optimizing timing closure, power integrity, and clock networks for AI, ML, and data center applications. Collaborate with cross-functional teams to deliver high-performance silicon solutions in a fast-paced semiconductor environment. Requires deep expertise in full-cycle physical design, scripting, and methodology improvements.

Key Highlights
Cutting-edge ASIC development for AI, ML, networking, and data center applications
Full-cycle physical design ownership from RTL synthesis to tape-out
High compensation with stock, bonus, and relocation assistance available
Key Responsibilities
Drive physical implementation activities throughout the ASIC development lifecycle, including RTL synthesis, place-and-route, and timing closure
Perform EM/IR analysis and optimize clock tree architectures for skew balancing and insertion delay improvements
Develop and refine floorplans, physical layouts, and methodology improvements for complex designs
Technical Skills Required
Physical Design (ASIC) RTL Synthesis TCL Scripting
Benefits & Perks
Health, dental, and vision insurance
401k with 6% match
Annual bonus (15-30%) and generous stock options
Flexible/Unlimited PTO
FSA and HSA
Life and disability insurance

Job Description

Physical IC Design Engineer (Senior, Staff or Principal level)

Locations: San Jose, CA or Colorado Springs, CO (relocation offered)

Compensation (base, bonus + stock):

Senior Engineer up to $280-300k, Staff up to $400k, Principal up to $580k

Introduction

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