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ASIC Engineering Lead (Physical Design/STA) – Senior Technical Leadership

CyberCoders • United State
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Lead end-to-end ASIC programs for advanced compute and infrastructure silicon, ensuring high-quality tape-outs and customer success. Guide technical teams, mitigate risks, and shape design methodologies for AI, HPC, networking, and storage applications. Requires deep expertise in physical design, STA, and semiconductor workflows with hands-on execution and leadership acumen.

Key Highlights
Senior technical leadership role with 80% hands-on execution and 20% strategic guidance for complex ASIC programs
Compensation up to $880k total (base + bonus + stocks) for Master Level, $550k for Principal Level
Focus on bleeding-edge AI and high-performance silicon with end-to-end ownership from RFQ to production
Key Responsibilities
Lead end-to-end customer ASIC programs, including RFQs, technology planning, IP integration, design, test, packaging, fabrication, bring-up, and production
Advise customer teams on EDA best practices, design flows, and methodologies, including hosting technical Q&A sessions
Identify and mitigate risks related to quality, schedule, or dependencies by coordinating with internal and external teams
Run physical design validation flows to ensure customer netlists meet strict tape-out quality requirements
Stay updated on new semiconductor technologies, IP developments, and application trends
Collaborate with marketing, sales, legal, and compliance teams on program-related discussions
Technical Skills Required
Physical Design (or Static Timing Analysis) Semiconductor Process Flows (Advanced Node Tape-outs) EDA Tools (Physical Design, Logic Simulation, Test, Packaging)
Benefits & Perks
Health, dental, and vision insurance
401k with match
Annual bonus (15-30%) and generous stock options
Life and disability insurance
FSA and HSA
Generous PTO
Visa sponsorship for qualified candidates
Nice to Have
Exposure to SERDES communication protocols
Logic design, chip architecture, or microarchitecture experience
Verilog RTL development and front-end verification
DFT methods (scan, memory BIST, repair)
Programming/scripting experience

Job Description

ASIC Engineering Lead (Physical Design OR STA)

Principal Level up to $550k, Master Level up to $880k total comp (base + bonus + stocks)

Locations: San Jose, CA, Irvine, CA or Fort Collins, CO

Introduction
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