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Master Physical Design Engineering Lead (Senior Technical Leadership)

United State
Visa Sponsorship
This Job is No Longer Active This position is no longer accepting applications

Lead end-to-end customer ASIC programs in advanced semiconductor design, ensuring successful delivery of complex physical design, STA, DFT, and packaging projects. Guide technical teams, mitigate risks, and shape industry-leading methodologies for AI, HPC, and high-performance silicon. Drive innovation in next-gen semiconductor technologies with a blend of hands-on execution and strategic leadership.

Key Highlights
Total compensation package up to $800,000 (base + bonus + stock)
Hands-on technical leadership with 80% execution and 20% strategic guidance
Focus on advanced compute, AI, and high-performance infrastructure silicon
Key Responsibilities
Lead end-to-end customer ASIC programs from RFQs through production, including technology planning, IP integration, design, test, packaging, fabrication, bring-up, and tape-out validation
Advise customer teams on EDA best practices, design flows, and methodologies, including hosting technical Q&A sessions with experts
Identify and mitigate risks related to quality, schedule, and dependencies by coordinating with internal and external teams
Technical Skills Required
Physical Design Engineering Static Timing Analysis (STA) Electronic Design Automation (EDA) Tools
Benefits & Perks
Health, dental, and vision insurance
Life and disability insurance
401k with match, FSA, HSA, ESPP, generous PTO, and annual bonus (15-30%)
Nice to Have
SERDES communication protocols
Logic design, chip architecture, or microarchitecture experience
Verilog RTL development, front-end verification, or DFT methods (scan, memory BIST, repair)

Job Description

Master Physical Design Engineering Lead (up to $800k package)

Total package up to $800k (Base + bonus + stock)

Locations: San Jose, CA, Irvine, CA or Fort Collins, CO

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