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RAS (Reliability, Availability, Serviceability) Architect

rosaiclabs inc
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AI Summary

RosaicLabs seeks a RAS Architect to define resilience across its multi-die computing systems, translating reliability targets into hardware, firmware, and software requirements for fault detection, error containment, recovery, silent-data-corruption prevention, and fleet telemetry. Core duties include owning end-to-end RAS specifications, defining fault detection/correction/logging across compute engines, caches, HBM/LPDDR, die-to-die links, and PCIe/CXL, specifying ECC and parity schemes, and driving error-injection and verification campaigns. Requires a Bachelor's degree in EE/CE/CS or equivalent, at least 12 years in SoC architecture or platform reliability with 3+ years leading RAS features, silicon bring-up experience, and cross-domain expertise spanning at least two of compute/cache, memory, interconnects, or high-speed links.

Key Highlights
Define end-to-end RAS specifications across multi-die computing systems including fault detection, error containment, and recovery
Specify ECC, parity, memory scrubbing, and silent-data-corruption prevention mechanisms
At least 12 years of experience in SoC architecture or platform reliability with 3+ years leading RAS features
Cross-domain expertise across compute/cache, memory, interconnects, or PCIe/CXL
Visa sponsorship available; benefits include Medical, Dental, Vision, Life & AD&D, and 401(k)
Key Responsibilities
Own end-to-end RAS specification, reliability and availability targets, FIT budget by domain, common error records and timestamps, and software-visible error-bank mapping
Define fault detection, correction, logging, and diagnosis across compute engines, caches, HBM and LPDDR memory, die-to-die links, PCIe/CXL, and management agents
Specify ECC, parity, residue checks, memory scrubbing, retirement or repair, and in-field screening to prevent and detect silent data corruption
Define end-to-end poison propagation, containment, retry, and recovery for correctable and uncorrectable errors crossing die or subsystem boundaries
Specify isolation, fencing, and degraded-operation behavior for compute units, cores/clusters, memory resources, links, and package-level failures
Define firmware-first error handling and reporting interfaces for drivers, OS, BMC, and fleet management including telemetry for predictive maintenance
Translate RAS requirements into implementable interfaces for error banks, poison paths, injection hooks, logging, and recovery controls
Define per-domain error-injection hooks, verification coverage, and campaigns for cross-domain faults in simulation, emulation, and silicon
Work with DFT, reliability, verification, firmware, and software teams on in-field screening, silicon debug, and analysis of production and fleet failures

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Technical Skills Required
SoC Architecture RAS (Reliability, Availability, Serviceability) Silicon Validation
Benefits & Perks
Medical (including HSA plans)
Dental
Vision
Employee Life & AD&D
401(k)

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Nice to Have
Familiarity with processor and uncore error-reporting architectures, firmware-first error handling, BMC integration, or fleet reliability telemetry
Experience with silent-data-corruption analysis, in-field screening, or graceful degradation of large multi-die systems
Ability to drive the microarchitecture of RAS logic blocks such as error banks, poison paths, injection controls, and recovery state machines

Job Description

RosaicLabs is seeking a Reliability, Availability, and Serviceability (RAS) Architect to define resilience across its multi-die computing systems. This person will turn reliability targets into hardware, firmware, and software requirements for fault detection, error containment, recovery, silent-data-corruption prevention, and actionable fleet telemetry.

Core Responsibilities

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Job Overview
Posted Nov 13, 2026
Employment Full-time
Experience Not Applicable
Category Programming
Company rosaiclabs inc
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