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Senior Digital Design Engineer (Verilog/SystemVerilog)

sitime • Netherlands
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AI Summary

Senior Digital Design Engineer role focused on RTL design, synthesis, and timing analysis for MEMS and Analog Semiconductor company in Delft, Netherlands. Requires 4+ years of experience in Verilog/SystemVerilog, digital logic design, and mixed-signal expertise. Master’s degree in electrical engineering or related field mandatory.

Key Responsibilities
Developing micro-architecture specifications and RTL designs using Verilog/SystemVerilog
Creating test benches and SystemVerilog Assertions (SVA) for design verification
Writing timing constraints and performing synthesis/STA using tools like Genus, Design Compiler, and Prime Time
Collaborating with cross-functional engineering teams for post-Si validation and debugging

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Technical Skills Required
Verilog/SystemVerilog RTL Design Static Timing Analysis (STA)

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Nice to Have
Experience with mixed-signal digital logic design
Basic knowledge of Discrete-time Signal Processing (FIR/IIR filters)
Scripting proficiency in Perl/Tcl/Python

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Job Description

A fantastic opportunity for an experienced Digital Design Engineer to join a MEMS and Analog Semiconductor company who offer the industry’s most advanced and most reliable timing solutions.

Responsibilities:

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Job Overview
Posted Nov 04, 2026
Employment Full-time
Experience Mid-Senior level
Location Netherlands
Category Programming
Company sitime
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