Senior Verification Engineer (UVM, SystemVerilog, Python, Perl, Bash, TCL)

European Tech Recruit • Spain

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AI Summary

Join a Spain-based semiconductor company as a Senior Verification Engineer. Requirements include MSc or PhD in a related field, 4+ years of experience, and proficiency in SystemVerilog, UVM, and scripting languages. Excellent salary, flexible work schedules, and career progression.

Key Highlights

Verification Engineer role

Spain-based semiconductor company

MSc or PhD in a related field required

Technical Skills Required

SystemVerilog UVM Python Perl Bash TCL

Benefits & Perks

Excellent yearly salary

Flexible work schedules

Good career progression

Job Description

Verification Engineer - UVM / SystemVerilog / Python / Perl / Bash / TCL

Are you a Mid to Senior level Senior Verification Engineer looking for you next challenge?
Have experience with SystemVerilog and UVM, plus scripting in Python, Perl, Bash, or TCL?
Want to join a very exciting Spain based semiconductor company?

If you can say to this, then please keep reading.

We're partnered with a genuinely exciting Barcelona HQ'd semiconductor organization and they're seeking a number of Mid-to-Senior Verification Engineers to join them on a permanent basis, working fully onsite in central Barcelona.

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