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Block Verification Technical Lead (ASIC/SoC) - Barcelona, Spain

hireroo • Spain
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AI Summary

Leads functional verification of critical ASIC/SoC blocks (System Control & Boot or System Router & Interconnect) from planning to tapeout signoff. Manages 3-4 engineers, develops UVM/SystemVerilog testbenches, drives coverage closure, and collaborates with RTL design teams. Requires 6+ years in ASIC/SoC verification with UVM expertise, leadership, and tapeout experience.

Key Highlights
Leads ASIC/SoC block verification from planning to tapeout signoff
Hybrid work model (4 days in office, 1 day remote)
Two specializations: System Control & Boot or System Router & Interconnect
Key Responsibilities
Own block verification plans, execution, and tapeout signoff
Develop and maintain SystemVerilog/UVM testbenches, reference models, and assertions
Drive functional coverage, regressions, debugging, and bug closure
Lead and mentor 3-4 verification engineers
Collaborate with RTL design teams on microarchitecture and interface verification
Improve regression automation, CI, and verification workflows

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Technical Skills Required
SystemVerilog UVM (Universal Verification Methodology) ASIC/SoC Functional Verification
Benefits & Perks
Flexible working hours
Hybrid model (4 days office, 1 day remote)
1 week per year working from anywhere
25 days annual leave plus December 24 and 31
Monthly food allowance
Private medical insurance
Relocation bonus
Housing search support
Visa support (subject to approval)
Family relocation support (subject to eligibility)
Virtual shares (subject to plan terms)
Language classes
Tax incentive

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Nice to Have
Experience with RISC-V, CPU clusters, or AI accelerators
Cache coherence protocols (CHI, ACE, MESI/MOESI)
GitLab CI and verification automation
Previous people management experience
Specialized experience in System Control (interrupt controllers, boot) or System Router (NoC, interconnects)

Job Description

Our partner is looking for two Block Verification Technical Leads to own functional verification of critical ASIC/SoC blocks, from verification planning through tapeout signoff.

Each position involves leading 3 to 4 verification engineers, developing SystemVerilog/UVM environments, driving coverage closure, and collaborating closely with RTL design teams.

We Are Recruiting For Two Technical Specializations

Position 1: System Control & Boot Verification

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Job Overview
Posted Nov 12, 2026
Employment Full-time
Experience Mid-Senior level
Location Spain
Category Programming
Company hireroo
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