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Reliability, Availability, and Serviceability (RAS) Architect

rosaiclabs inc • United States
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AI Summary

RosaicLabs seeks a RAS Architect to define resilience across multi-die computing systems through hardware, firmware, and software requirements. Own fault detection, error containment, recovery, silent-data-corruption prevention, and fleet telemetry specification end-to-end. Requires 12+ years in SoC architecture, design, verification, or platform reliability, including 3+ years leading RAS features.

Key Highlights
Own end-to-end RAS specification including reliability, availability targets, FIT budget, and error-bank mapping
Define fault detection, correction, logging, and diagnosis across compute, memory, interconnects, and management agents
Specify ECC, parity, memory scrubbing, and in-field screening to prevent silent data corruption
Lead firmware-first error handling interfaces for drivers, OS, BMC, and fleet management telemetry
Require 12+ years in SoC architecture/validation with 3+ years leading RAS features

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Key Responsibilities
Own the end-to-end RAS specification, reliability and availability targets, FIT budget by domain, common error records and timestamps, and software-visible error-bank mapping
Define fault detection, correction, logging, and diagnosis across compute engines, cores, caches, HBM, LPDDR memory, die-to-die links, PCIe/CXL, and management agents
Specify ECC, parity, residue checks, memory scrubbing, retirement, repair, and in-field screening to prevent and detect silent data corruption
Define end-to-end poison propagation, containment, retry, and recovery for correctable and uncorrectable errors across die or subsystem boundaries
Specify isolation, fencing, and degraded-operation behavior for compute units, cores, clusters, memory resources, links, and package-level failures
Define firmware-first error handling and reporting interfaces for drivers, the OS, BMC, and fleet management including telemetry for predictive maintenance
Translate RAS requirements into implementable interfaces for error banks, poison paths, injection hooks, logging, and recovery controls
Define per-domain error-injection hooks, verification coverage, and campaigns for cross-domain faults in simulation, emulation, and silicon
Work with DFT, reliability, verification, firmware, and software teams on in-field screening, silicon debug, and analysis of production and fleet failures
Technical Skills Required
SoC Architecture Error Handling and Containment Silicon Validation

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Benefits & Perks
Medical (including HSA plans)
Dental
Vision
Employee Life & AD&D
401(k)

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Nice to Have
Familiarity with processor and uncore error-reporting architectures, firmware-first error handling, BMC integration, or fleet reliability telemetry
Experience with silent-data-corruption analysis, in-field screening, or graceful degradation of large multi-die systems
Ability to drive the microarchitecture of RAS logic blocks such as error banks, poison paths, injection controls, and recovery state machines

Job Description

RosaicLabs is seeking a Reliability, Availability, and Serviceability (RAS) Architect to define resilience across its multi-die computing systems. This person will turn reliability targets into hardware, firmware, and software requirements for fault detection, error containment, recovery, silent-data-corruption prevention, and actionable fleet telemetry.

Core Responsibilities

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Job Overview
Posted Nov 12, 2026
Employment Full-time
Experience Mid-Senior level
Location United States
Category Programming
Company rosaiclabs inc
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