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Senior Digital Verification Engineer (Mixed-Signal ASICs, Neurotechnology)

careerjet • United Kingdom
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AI Summary
Key Highlights
First Verification expert in a pioneering neurotechnology/medical ASIC team
Own verification strategy from block-level to full-chip sign-off and silicon bring-up
Collaborate with analogue teams on mixed-signal interfaces and safety validation

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Key Responsibilities
Define and lead digital verification strategy for mixed-signal ASICs, including testbench development (UVM/SystemVerilog), coverage closure, and tape-out sign-off.
Develop reusable testbenches, constrained-random stimulus, assertions, and scoreboards for digital subsystems.
Execute verification through simulation regressions, RTL debugging, and automation using Python/Tcl/Shell.
Collaborate with analogue teams on mixed-signal verification, safety mechanisms, and fault injection.
Support post-silicon bring-up, lab testing, and hardware-software correlation.

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Technical Skills Required
SystemVerilog/UVM verification ASIC digital verification (mixed-signal) Python/Tcl/Shell scripting

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Job Description

This is an opportunity to take a technically influential role within a growing semiconductor business, working on complex mixed-signal ASIC technology for a highly innovative medical application.

I am working with an innovative, early-stage technology company operating at the intersection of neurotechnology and semiconductor engineering. They are developing advanced IC solutions for implantable medical devices, designed to support the management and treatment of neurological conditions.

The Role

As a Senior Digital Verification Engineer, you will take ownership of the verification strategy and execution for the digital subsystems within next-generation mixed-signal ASICs.

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Job Overview
Posted Nov 09, 2026
Employment Full-time
Experience Mid-Senior level
Location United Kingdom
Category Programming
Company careerjet
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