Senior Package Layout Engineer (AI Hardware Accelerators)

Acceler8 Talent • United State

Visa Sponsorship

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AI Summary

Lead end-to-end physical design and development of advanced 2.5D/3D semiconductor packages for next-gen AI accelerators, collaborating with cross-functional teams to optimize high-performance, high-density layouts, power/ground networks, and signal integrity. Requires 8+ years of expertise in package substrate/interposer design, routing, and verification for high-bandwidth memory and heterogeneous multi-die systems. Must leverage industry-standard tools and drive manufacturability while resolving complex design challenges.

Key Highlights

End-to-end ownership of 2.5D/3D multi-die package layouts for AI accelerators, including stackup definition, bump mapping, RDL routing, and tapeout release

Collaboration with silicon, PCB, and packaging teams to ensure high-performance, high-bandwidth memory (HBM) and power integrity

Development and optimization of AI-assisted design tools for routing, verification, and signoff

Key Responsibilities

Own end-to-end package substrate and interposer layout, including stackup definition, bump/ball mapping, RDL routing, and high-density escape routing

Design and optimize multi-die 2.5D/3D packages supporting HBM interfaces and high-performance accelerator silicon

Develop power/ground distribution networks for high-current accelerator requirements and drive die-to-package-to-board co-design

Perform package DRC, LVS, and netlist verification while collaborating with OSAT partners and substrate suppliers

Resolve complex routing, signal/power integrity, and manufacturability challenges using AI-assisted design tools

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Technical Skills Required

Advanced 2.5D/3D Semiconductor Packaging Package Substrate & Interposer Layout Signal/Power Integrity Optimization

Benefits & Perks

Visa sponsorship for eligible candidates (H-1B, O-1, TN, E-3, F-1 OPT, STEM OPT)

Compensation dependent on experience and role level

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Nice to Have

Experience with AI accelerator, GPU, or high-performance processor packaging

Familiarity with HBM integration, chiplet architectures, and heterogeneous multi-die systems

Background working directly with semiconductor substrate suppliers and OSAT partners

Automation/scripting experience for package layout, routing, and verification

Job Description

Package Layout Engineer

Location: Mountain View, CA

Onsite

About the Role

An innovative AI hardware startup is seeking an experienced Package Layout Engineer to own the physical design and development of advanced semiconductor packages for next-generation AI accelerators.

This role offers end-to-end ownership of complex 2.5D and 3D multi-die package layouts, from initial bump mapping and stackup definition through substrate routing, interposer design, verification, and tapeout release.

You'll work closely with silicon physical design, signal and power integrity, PCB layout, and packaging teams to develop high-performance packages supporting advanced AI computing systems.

Key Responsibilities

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