Senior Machine Learning Engineer (LLM Post-Training & Evaluation for EDA)

d24 search • United State

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AI Summary

Join a cutting-edge AI-driven EDA startup to develop and optimize large language models for chip design and verification. Focus on fine-tuning, evaluation, and productionizing models that accelerate RTL debugging and verification workflows. Requires expertise in LLM post-training, EDA-specific ML, and collaboration with research and engineering teams.

Key Highlights

Develop and fine-tune LLMs for chip design and verification tasks using advanced techniques like supervised fine-tuning and reinforcement learning.

Build and maintain scalable data pipelines for training, including data collection, cleaning, and synthetic data generation.

Collaborate with cross-functional teams to bring research-driven models into production with real-world impact.

Key Responsibilities

Train, fine-tune, and post-train LLMs for chip design and verification tasks using supervised fine-tuning and reinforcement learning.

Design and implement evaluation frameworks and benchmarks to measure model accuracy, reliability, and agent performance on real engineering workflows.

Build and maintain data pipelines for training, including data collection, cleaning, and synthetic data generation.

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Technical Skills Required

Large Language Model (LLM) Post-Training (SFT, RLHF) Machine Learning for Electronic Design Automation (EDA) Data Pipeline Development

Benefits & Perks

Up to $350,000 + Equity

Visa transfers supported

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Nice to Have

Experience partnering with customers to gather product requirements and productize technical solutions

Systems and inference-level understanding (C++, CUDA, GPU architecture, SGLang, vLLM, model deployment and optimization strategies)

Job Description

Machine Learning Engineer

Santa Barbara, CA

Up to $350K + Equity

Visa transfers ok

My client is a well funded AI – Driven EDA start up revolutionizing the chip design and verification process with agentic AI tools tailored for the semiconductor industry.Thier flagship , leverages advanced AI agents to streamline and enhance the design, debugging, and verification of RTL (Register Transfer Level) code, accelerating time-to-market for chip developers.

We are committed to empowering hardware design and verification engineers by providing cutting-edge solutions that improve efficiency, scalability, and accuracy in chip development.

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