Principal ASIC Engineering Lead (Physical Design/STA) – Advanced Semiconductor & AI Chip Development
Lead end-to-end ASIC programs for AI, HPC, and high-performance silicon, blending technical expertise in physical design, STA, and DFT with strategic guidance for customers and internal teams. Drive tape-out quality, risk mitigation, and cutting-edge design methodologies while collaborating cross-functionally. Leverage deep semiconductor knowledge to shape next-gen semiconductor technologies with a focus on performance, power, and area optimization.
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Job Description
Principal ASIC Engineering Lead (Physical Design OR STA)
Up to $230k base, + 30% bonus plus around $800k-$1.2m in stocks which vests 1/16th every quarter for 4 years
Total first year realistic income $450-500k
Locations: San Jose, CA, Irvine, CA or Fort Collins, CO
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