Lead verification strategy and closure for world-class SoCs in AI and HPC networking solutions. Develop UVM-based testbenches, functional tests, and drive coverage closure at block, subsystem, and SoC levels. Requires 8+ years of hands-on experience with UVM/SystemVerilog, complex SoC verification, and simulation/debug tools.
Key Highlights
Lead verification closure for entire projects including design modules, sub-systems, and SoCs
Drive UVM testbench development, test planning, regression, and coverage closure
Provide day-to-day guidance and leadership to verification team members
Collaborate with cross-functional teams including design, software, emulation, and silicon validation
Experience with AI tools to generate test plans and improve verification productivity is highly desirable
Key Responsibilities
Define overall SoC level verification strategy, technical planning, and direction
Enable and drive the development of UVM environments to verify RTL at block, unit, and SoC levels
Develop and execute functional tests according to verification test plans
Instrument testbenches for functional and code coverage and drive to closure based on coverage metrics
Collaborate with cross-functional teams including design, software, emulation, and silicon validation teams
Provide day-to-day guidance and leadership of team members
Drive results via mentoring, coaching, and counseling
Educate team in the use of AI tools to enhance productivity and efficiencies
Generate and enforce coding and verification guidelines
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Benefits & Perks
Equity and cash compensation
Health, dental, and vision coverage
401(k) with company match
Open Time Off (OTO)
Performance-based incentives and annual bonus
Disability and life insurance
Dependent care flexible spending account
Pet insurance
Paid holidays and sick time
Bonding leave and pregnancy disability leave
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Nice to Have
M.S. Degree in Computer Engineering, Computer Science, or Electrical Engineering
8+ years of relevant experience in networking hardware verification
Proven expertise in verifying 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSec
One or more scripting languages (TCL, Python, Perl, Shell-scripting)
Track record of first-pass success in ASIC and Systems
Experience utilizing AI tools to generate test plans and improve verification productivity
