Chief Engineer: RISC-V Architecture, Multi-Orbit NTN Regenerative Payload

We're Hiring: Chief Engineer: RISC-V Architecture, Multi-Orbit NTN Regenerative Payload

📍 Abu Dhabi, UAE | Full-Time | Space & Defense Sector

Apply at : www.sraut.tech/join or email: [email protected] 

Role Overview:

Own the end-to-end architecture of our Regenerative Payload, from algorithm development and SDR validation through FPGA prototyping, RISC-V/SoC development, radiation-hardened ASIC design, and flight qualification. 

Key Responsibilities:

Algorithm Development: Design and validate PHY/MAC algorithms for multi-orbit NTN scenarios before hardware commitment.

SDR Validation: Implement and validate multi-orbit NTN algorithms on SDR platforms, demonstrating real-time performance under representative satellite-channel conditions.

RISC-V Architecture & RTL: Define RISC-V microarchitecture and develop RTL using SystemVerilog or Chisel.

Custom Instructions: Design RISC-V extensions for core IP. Modify GCC/LLVM/Clang compiler backends and the Instruction Set Simulator.

ISS & Golden-Model Verification: Establish a software ISA reference model using Spike or equivalent, enabling RTL validation against known-correct golden results before silicon.

Functional Verification: Lead verification using SystemVerilog/UVM and/or cocotb, with simulators such as Verilator/Icarus.

FPGA Prototyping: Implement validated algorithms and RTL on FPGA and demonstrate the complete RISC-V+ accelerator SoC before tape-out.

Firmware & Protocol Stack: Oversee C/C++ firmware and RTOS software for RISC-V, including MAC, RLC, PDCP & RRC using RISC-V GCC or LLVM/Clang toolchains.

EDA & Automation: Own or oversee scripting and automation for synthesis, place-and-route. RTL to manufacturable layout.

Rad-Hard ASIC: Lead migration from FPGA prototype to radiation-hardened ASIC, including tape-out, fabrication readiness, and space qualification.

Required Qualifications:

10+ years in communications systems, SoC, or related engineering, with experience spanning algorithm/simulation through SDR/FPGA prototyping and silicon.

Strong hands-on programming across hardware and software development.

Proven experience with RISC-V custom instruction extensions, including compiler backend and ISS modification.

Functional verification experience with UVM and/or cocotb, preferably using Verilator/Icarus.

Hands-on SDR development experience.

Strong knowledge of 3GPP Release18/19 and beyond, preferably NTN.

Experience or strong working knowledge of radiation-hardened design for space applications.

Proven engineering-team leadership experience.

Bachelor's/Master's in EE, CE, Computer Engineering, or related field; PhD is a plus.

Highly Desired:

Contributions to open RISC-V projects such as Rocket, BOOM, CVA6, or Shakti.

Experience with Yosys/OpenROAD and other EDA flows or rad-hard FPGA platforms.

Experience with satellite payloads, D2D satellite systems, or defense-grade communications hardware.

Familiarity with orbital and satellite-channel simulation tools for multi-orbit link modeling.

Note: Work Permit Sponsorship is available for qualified candidates.