Senior Verification Engineer (UVM/SystemVerilog)

Senior Verification Engineer

Oxford, UK

This is a unique opportunity to join an innovative quantum technology company as one of the first UVM Verification Engineers within its growing Oxford team.

You will have significant autonomy and the opportunity to take ownership of the verification environment, helping to define the methodology, infrastructure and best practices used across the team.

The company is developing advanced quantum computing systems, and the role offers an unusual combination of working within a fast-paced, start-up-style environment while benefiting from the backing and resources of a global organisation.

You will work at the intersection of FPGA development and quantum technology, helping to develop and verify the sophisticated control systems that underpin next-generation quantum computing platforms.

The Role

As a Senior Verification Engineer, you will play a key role in developing the verification environments and methodologies used across complex FPGA designs.

Working closely with FPGA and RTL Design Engineers, you will take ownership of verification infrastructure and help establish best practices across simulation, verification and test.

Key responsibilities will include:

• Architecting, developing and maintaining advanced UVM/SystemVerilog verification environments for complex FPGA designs.
• Defining and executing comprehensive verification plans.
• Developing constrained-random test environments and driving functional and code coverage closure.
• Working closely with RTL Design Engineers to debug failures, identify root causes and improve overall design quality.
• Developing and maintaining automated regression environments.
• Supporting continuous integration and verification workflows throughout the FPGA development lifecycle.
• Helping define and drive verification methodology and best practices across the wider FPGA team.

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Requirements

This role would suit an engineer with approximately 4–7 years of professional experience within an FPGA or ASIC verification environment and a strong background in modern verification methodologies.

Key experience includes:

• Strong SystemVerilog and UVM experience.
• Experience architecting and developing verification environments.
• Constrained-random and coverage-driven verification experience.
• Verification planning and requirements gathering.
• Python for scripting and test automation.

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• Strong debugging and problem-solving skills.
• Experience working closely with RTL and/or FPGA design teams.

This would particularly suit a Verification Engineer who wants to move into a position with greater ownership and autonomy, helping to shape verification architecture and methodology rather than simply working within an established environment.

On offer is a competitive base salary, RSUs and bonus.

Visa sponsorship and relocation support can be provided for engineers who are already living and working in the UK and require support to move to Oxford.

Unfortunately, relocation and visa sponsorship for candidates currently based outside the UK are not available at this time.