Join a leading semiconductor team in Tokyo as a DFT Engineer, Senior DFT Engineer, Staff DFT Engineer, or DFT Manager. Lead ASIC/SoC DFT, ATPG, BIST, JTAG, and scan compression with hands-on experience in validation, debug, and full-chip integration. Visa sponsorship and relocation support available for international candidates.
Key Highlights
Key Responsibilities
Technical Skills Required
Benefits & Perks
Nice to Have
Job Description
DFT ENGINEER / SENIOR DFT ENGINEER / STAFF DFT ENGINEER / DFT MANAGER
Tokyo, Japan | Onsite | Permanent
Visa Sponsorship & Relocation Support Available.
We are looking for experienced Design for Test (DFT) professionals to join a leading semiconductor engineering team in Tokyo, Japan.
This is an excellent opportunity for professionals with strong hands-on experience in ASIC/SoC DFT, ATPG, Scan, BIST, JTAG, pattern generation and coverage analysis.
OPEN POSITIONS:
DFT Engineer – 3+ years
Senior DFT Engineer – 5+ years
Staff DFT Engineer – 5+ years
DFT Manager – 8+ years
KEY RESPONSIBILITIES:
Scan insertion, validation & debug – block/full-chip
ATPG & pattern generation/validation
MBIST / LBIST / BIST implementation
Scan compression & scan-chain insertion
JTAG / Boundary Scan / BSDL
Stuck-at, Transition, IDDQ & memory/e-Fuse patterns
DFT mode timing analysis & sign-off
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Fault & coverage analysis
Gate-level pattern simulation & debugging
Full-chip DFT integration & verification
Post-silicon debug support
Automation using Perl & TCL
Collaboration with RTL, Synthesis, STA & Physical Design teams
DFTMAX, TetraMAX, VCS
Genus, Modus, Xcelium
Tessent, TestKompress
SpyGlass
REQUIRED SKILLS:
Strong hands-on experience in several of the following:
Scan Insertion | ATPG | MBIST | LBIST | BIST | JTAG | Boundary Scan | BSDL | Scan Compression | Pattern Validation | Coverage Analysis | DFT Timing Analysis
Additional experience with:
Verilog & RTL simulation
ASIC/SoC design & verification flows
Block-level & full-chip DFT
Gate-level simulation & debug
Perl & TCL scripting
Post-silicon debug – advantageous
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JAPANESE LANGUAGE REQUIREMENT:
For the initial hiring requirement, 5 candidates with Japanese communication skills are sought.
JLPT N3/N4 or equivalent conversational Japanese is preferred.
Candidates do not need to be currently located in Japan.
International candidates are welcome.
Japan visa sponsorship and relocation support are available.
After the initial five bilingual hires, non-Japanese-speaking DFT candidates may also be considered.
COMPENSATION
Salary is negotiable and will depend on:
DFT experience & technical expertise
Seniority
Current compensation
Japanese language ability
JOINING
Immediate / early joiners preferred.
Candidates with notice periods of approximately 2–3 months can also be considered, taking visa and relocation processing into account.
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