Design and architect the RTL for a high-performance AI accelerator, owning digital blocks from microarchitecture to silicon. Implement synthesizable SystemVerilog, optimize PPA targets, and collaborate across DV, PD, and DFT. Requires 5+ years of complex digital design experience with strong RTL, synthesis, and timing expertise.
Key Highlights
End-to-end ownership of digital blocks (compute datapath, memory, interconnect, control logic) for an AI accelerator
Translate microarchitecture specs into synthesizable, timing-clean RTL with PPA optimization
Collaborate with verification, physical design, and DFT teams from RTL to tapeout
Key Responsibilities
Design and implement RTL for compute datapath, memory subsystems, on-chip interconnect, and control logic
Define microarchitecture trade-offs (pipelining, datapath vs. control, clock/power gating) for high-performance, low-power designs
Translate architectural specs into synthesizable RTL, ensuring PPA targets are met via SDC, STA, and lint signoff
Collaborate with verification engineers on block-level testing, physical design for synthesis/timing closure, and DFT for testability
Debug and validate designs across simulation, emulation, and post-silicon bring-up
Develop and leverage AI-assisted tool flows to accelerate design and verification processes
Technical Skills Required
SystemVerilog
Digital Microarchitecture Design
Synthesis & Timing Optimization
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Benefits & Perks
Equity grant per company guidelines
Medical, dental, and vision insurance
401(k) retirement plan with standard PTO
Nice to Have
AI/ML accelerator or high-performance compute datapath design experience
Low-power techniques (UPF) and high-speed interfaces (HBM, PCIe, SerDes)
Experience with advanced nodes (7nm or better) or RISC-V/CPU design
FPGA prototyping knowledge
Job Description
Design the RTL that defines our AI accelerator. You'll architect and implement the digital blocks — compute datapath, memory subsystem, on-chip interconnect, and control logic — from microarchitecture spec through synthesis-ready, timing-clean RTL, and own those blocks end-to-end with architecture, DV, physical design, and DFT all the way to silicon.
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