FPGA Developer with TS/SCI & Full-Scope Polygraph - Fort Meade, MD

US Citizens only, Those willing to work in, reside in/near Fort Meade MD may be considered 1st. Schedule may be 9/80, Relocation Assistance may be Available - Possible for ideal candidate

Please read the entire job description and be a perfect/strong fit. US CITIZENS ONLY W TS/SCI & CI or FS POLY

Would you please call 860 889 4141 until 8PM EST 7 days a week as you can take notes & after you email your resume to

[email protected]

GRAZIE

Joe

FPGA Developer The critical requirement for this role is an active TS/SCI clearance with a Full-Scope Polygraph. However, we may have the flexibility to consider candidates who hold a CI Polygraph for this contract.

The position involves supporting both FPGA development and hardware reverse engineering efforts.

We are looking for a customer-focused team player working on-site in a mission-oriented environment. The candidate must be a self-starter, possess good communication skills, and be willing to interface with multiple teams throughout the design process.

We are looking for a direct hire W2 candidate. The candidate needs to have 4+ years of experience with FPGA design. Our base salary is up to $250k based on experience + 15% 401k.

We are currently seeking FPGA design engineers with emphasis on FPGA or ASIC design, development and verification using SystemVerilog, Verilog or VHDL. The design engineer will work closely with software and system engineers to conceptualize, document, design, code, verify and lab-debug ASIC, FPGA and embedded firmware designs. The ideal candidate will be adaptable, motivated, customer oriented, able to lead a small team and willing to mentor others while learning about new technologies.

Qualifications:

● Must currently possess an active TS/SCI Clearance with Full-Scope Polygraph (FSP). or CI poly

Experience using VHDL RTL Coding (for design and/or analysis of digital circuits)

● Experience with FPGA Design, synthesis, P&R tools (ex Vivado, Quartus)

● Experience utilizing Verilog/System and Verilog test bench development

● Experience working with Linux/Windows OS

● Knowledge of design simulation tools (Mentor, Cadence, Synopsys - 1 or more)

● Strong oral/written communication

● Location is onsite at Fort Meade, MD.

You Could Also Have This

● Experience with Verilog RTL Coding

● Experience using soft/hard IP cores in FPGAs/ASICs (ex Zynq or Microblaze or RISC processors, memories, flash/NVM)

● Experience in Reverse Engineering of digital designs from one or more levels of abstraction (ex from images of deprocessed hardware, GDS2 data, netlists, etc.)

● Knowledge of ASIC implementation methods/tools (synthesis, physical layout - Cadence/Synopsys)

● Knowledge of formal verification tools

● Knowledge of semiconductor manufacturing processes

● C/C++, Python, Perl or scripting

Education/Experience:

Multiple openings for Junior, Senior, Principal and Sr. Principal Engineers: Minimum three (3) years’ experience as a Design Engineer in integrated circuit or microelectronic component design or reverse engineering of the same is required. Bachelor’s degree in electrical engineering or computer engineering from an accredited college or university is required. Five (5) years of additional hardware design engineering experience may be substituted for a bachelor’s degree.

Our benefits include employer paid medical, dental and vision insurance, 25 days of paid time off, 11 government holidays, excellent 401K (6% employer contribution and 9% profit sharing), and flexible work schedule and comp time policy.