Digital Verification Manager-Jasper / VC_Formal /Microcontroller /Sub-System

Digital Verification Manager-Jasper / VC_Formal /Microcontroller /Sub-System

We are partnered up with a well-established Global Semiconductor organisation who are looking for a Digital Verification Manager to join their team in Ireland.

If this is you please continue reading below!

Responsibilities:

• Develop verification plans and execute them to achieve tape-out quality within specified timelines.
• Deploying advanced verification methodologies such as Universal Verification Methodology (UVM) and Formal Verification.
• testbenches and verification components, including Universal Verification Components (UVCs), C models, and reusable verification environments.
• Ensure comprehensive coverage and collaborate with design teams to address any coverage gaps.

Relocation and visa sponsorship is available if you are Europe!

• 8+ years of ASIC design verification experience, preferably with UVM-based functional verification.
• Familiarity with ARM or RISC-V ISA verification.
• formal verification tools like Jasper or VC_Formal is a plus.
• Microcontroller/Sub-System Experience.
• Power-Aware Verification:
• Proficiency in UVM, System Verilog, and Perl/Python shell

If interested Apply via LinkedIn, or send your CV to [email protected]

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